EP910DC-30 vs EP910DC-15 Vergleich
Detaillierter Direktvergleich von EP910DC-30 von Intel und EP910DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910DC-30 | EP910DC-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,60 | $10,75 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | — |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 12 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Versorgungsspannung | 5 V | — |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | — |
| Gehäuse | DIP-40 (through-hole, 600 mil) | 24-pin ceramic DIP (DC) |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Montageart | Through-Hole | Through-Hole |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Technology | — | CMOS EPROM, UV-erasable |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| RoHS-Status | — | [DATA_NEEDED: not explicitly stated in verified data] |