EP910DC-30 vs EP910IDC-15 Comparison
Detailed side-by-side comparison of EP910DC-30 by Intel and EP910IDC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-30 | EP910IDC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Classic EPLD |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | — |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 10 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Supply Voltage | 5 V | — |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | — |
| Package | DIP-40 (through-hole, 600 mil) | 40-pin CDIP (Ceramic DIP, through-hole) |
| Operating Temperature | 0C to +70C (commercial) | — |
| Mounting Type | Through-Hole | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Programming Technology | — | EPROM (UV-erasable) |
| RoHS Status | — | non_compliant (ceramic DIP contains lead) |