EP910DC-40 vs EP910JC-35 Comparison
Detailed side-by-side comparison of EP910DC-40 by Altera and EP910JC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-40 | EP910JC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.95 | $9.95 |
| Device Family | Classic EPLD (EP910 series) | β |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | β |
| Bidirectional I/O Pins | 24 | β |
| Total Inputs to Logic Array | 36 | β |
| Product Terms | 240 maximum | β |
| Maximum Propagation Delay (tPD) | 40 ns | β |
| Maximum Operating Frequency (fMAX) | 25 MHz | β |
| Global Clocks | 2 | β |
| Supply Voltage | 5 V (typical for Classic EPLD family) | β |
| Operating Temperature (Commercial) | 0 Β°C to 70 Β°C | β |
| Package | DIP-40 (ceramic, through-hole) | β |
| Mounting Type | Through-Hole | Surface Mount (PLCC socket recommended) |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: rohs status] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | β |
| Logic Family | β | Classic EPLD (CMOS EPROM) |
| Inputs | β | 36 |
| I/O Pins | β | 24 |
| Propagation Delay (max) | β | 38 ns (tPD) |
| Maximum Clock Frequency | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Operating Temperature | β | 0C to 70C (Commercial) |
| Package Type | β | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Terminal Form | β | J BEND |
| Package Code | β | QCCJ |
| Package Shape | β | SQUARE |
| Technology | β | CMOS EPROM, UV-erasable / OTP |
| Temperature Grading | β | COMMERCIAL |
| Equivalent Gates | β | Approx. 900 usable gates |