EP910DC-40 vs EP910JC-35 Comparison
Detailed side-by-side comparison of EP910DC-40 by Altera and EP910JC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-40 | EP910JC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Supply Voltage | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Package | DIP-40 (ceramic, through-hole) | — |
| Mounting Type | Through-Hole | Surface Mount (PLCC socket recommended) |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: rohs status] |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | — |
| Logic Family | — | Classic EPLD (CMOS EPROM) |
| Inputs | — | 36 |
| I/O Pins | — | 24 |
| Propagation Delay (max) | — | 38 ns (tPD) |
| Maximum Clock Frequency | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Operating Temperature | — | 0C to 70C (Commercial) |
| Package Type | — | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Terminal Form | — | J BEND |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Technology | — | CMOS EPROM, UV-erasable / OTP |
| Temperature Grading | — | COMMERCIAL |
| Equivalent Gates | — | Approx. 900 usable gates |