EP910IDC-15 vs EP910ILC-25 Comparison
Detailed side-by-side comparison of EP910IDC-15 by Altera and EP910ILC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IDC-15 | EP910ILC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | EP910 Classic EPLD |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package | 40-pin CDIP (Ceramic DIP, through-hole) | 44-pin JLCC (windowed ceramic) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 10 | — |
| Programming Technology | EPROM (UV-erasable) | — |
| RoHS Status | non_compliant (ceramic DIP contains lead) | non_compliant (ceramic windowed package) |
| User I/O Pins | — | 36 |
| Propagation Delay (tPD) | — | 25 ns |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Mounting Type | — | Surface Mount |
| Operating Temperature | — | -40C to +85C (industrial) |
| Supply Voltage | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Lifecycle Status | — | Obsolete - last time buy was late 1990s |