EP910ILC-12 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910ILC-12 by Intel and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-12 | EP910DC-30 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | Classic EPLD (EP910 series) |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | — |
| Propagation Delay (tPD) | 12 ns (max) | 30 ns (max) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| Package | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | DIP-40 (through-hole, 600 mil) |
| Mounting Type | Surface Mount | Through-Hole |
| Operating Temperature | -40 °C to +85 °C (industrial grade, 'I' suffix) | 0C to +70C (commercial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | UV-Erasable / OTP |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Number of Pins | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Macrocells | — | 24 |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Dedicated Inputs | — | 36 |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Supply Voltage | — | 5 V |
| Process Technology | — | CMOS |