EP910ILC-12 vs EP910IDC-15 Comparison
Detailed side-by-side comparison of EP910ILC-12 by Intel and EP910IDC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-12 | EP910IDC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | Classic EPLD |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | — |
| Propagation Delay (tPD) | 12 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| Package | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | 40-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Surface Mount | — |
| Operating Temperature | -40 °C to +85 °C (industrial grade, 'I' suffix) | — |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | non_compliant (ceramic DIP contains lead) |
| Number of Pins | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Macrocells | — | 24 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Dedicated Inputs | — | 10 |
| Programming Technology | — | EPROM (UV-erasable) |