EP910ILC-50 vs EP910ILC-15N Comparison
Detailed side-by-side comparison of EP910ILC-50 by Intel and EP910ILC-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoleteSpecification Comparison
| Parameter | EP910ILC-50 | EP910ILC-15N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic |
| Macrocells | 24 | — |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 24 | 36 |
| Dedicated Input Pins | 12 | 16 |
| Package | PLCC-44 (J-lead) | PLCC-44 (J-lead, surface mount) |
| Mounting Type | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | — |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 |
| Macro Cells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 66.6 MHz |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |