EP910ILC-50 vs EP910ILC-25 Comparison
Detailed side-by-side comparison of EP910ILC-50 by Intel and EP910ILC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILC-50 | EP910ILC-25 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD | EP910 Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| User I/O Pins | 24 | 36 |
| Dedicated Input Pins | 12 | — |
| Package | PLCC-44 (J-lead) | 44-pin JLCC (windowed ceramic) |
| Mounting Type | Surface Mount (socket-compatible) | Surface Mount |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM (UV-erasable) |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | non_compliant (ceramic windowed package) |
| Propagation Delay (tPD) | — | 25 ns |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Supply Voltage | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Lifecycle Status | — | Obsolete - last time buy was late 1990s |