EP910ILI-25 vs EP910ILC-50 Comparison
Detailed side-by-side comparison of EP910ILI-25 by Altera and EP910ILC-50 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILI-25 | EP910ILC-50 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.25 | $10.85 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Series | EP910 (Classic EPLD) | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | β |
| I/O Pins | 24 | β |
| Product Terms | 240 (maximum) | β |
| Propagation Delay (tPD) | 25 ns | β |
| Technology | CMOS, EPROM | CMOS EPROM, UV-erasable |
| Architecture | PAL-type with global interconnect bus | β |
| Package | PLCC-44 (windowed ceramic, J-lead) | PLCC-44 (J-lead) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | β |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | β |
| Logic Test Circuitry | On-board JTAG-compatible test | β |
| RoHS Status | Non-compliant (windowed ceramic package) | [DATA_NEEDED: RoHS compliance status] |
| Family | β | Altera Classic EPLD |
| Usable Gates | β | 900 (typical) |
| Maximum Frequency | β | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | β | 50 ns |
| Supply Voltage (VCC) | β | 5 V (typical) |
| User I/O Pins | β | 24 |
| Dedicated Input Pins | β | 12 |
| Mounting Type | β | Surface Mount (socket-compatible) |
| Programming Cycles | β | 100 (minimum) |
| Boundary Scan | β | IEEE 1149.1 JTAG (selected speed grades) |