EP910ILI-25 vs EP910ILC-50 比較
詳細並排比較 EP910ILI-25 由 Altera 與 EP910ILC-50 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILI-25 | EP910ILC-50 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | — |
| Technology | CMOS, EPROM | CMOS EPROM, UV-erasable |
| Architecture | PAL-type with global interconnect bus | — |
| 封裝 | PLCC-44 (windowed ceramic, J-lead) | PLCC-44 (J-lead) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| 工作溫度 | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | — |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| RoHS 狀態 | Non-compliant (windowed ceramic package) | [DATA_NEEDED: RoHS compliance status] |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Supply Voltage (VCC) | — | 5 V (typical) |
| User I/O Pins | — | 24 |
| Dedicated Input Pins | — | 12 |
| 安裝類型 | — | Surface Mount (socket-compatible) |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |