EP910IPC-15 vs EP910LI-20 Comparison
Detailed side-by-side comparison of EP910IPC-15 by Altera and EP910LI-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-15 | EP910LI-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | Sum-of-products macrocell |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 16 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Operating Temperature | 0C to +70C (commercial, IPC suffix) | -40C to +85C (Industrial) |
| Package | PDIP-40 (Plastic DIP, 40-pin) | 40-pin Ceramic DIP (Windowed) |
| Mounting Type | Through-Hole | — |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| Pin Count | 40 | 40 |
| RoHS Status | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: RoHS status] |
| Family | — | Altera Classic EPLD |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| Technology | — | CMOS, UV-erasable |
| Package Type | — | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | — | Industrial (-40C to +85C) |
| Logic Family | — | EPLD (Erasable PLD) |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |