EP910IPC-15 vs EP910LI-20 Comparaison
Comparaison détaillée côte à côte de EP910IPC-15 par Altera et EP910LI-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910IPC-15 | EP910LI-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,95 | $19,95 |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | Sum-of-products macrocell |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 16 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Température de fonctionnement | 0C to +70C (commercial, IPC suffix) | -40C to +85C (Industrial) |
| Boîtier | PDIP-40 (Plastic DIP, 40-pin) | 40-pin Ceramic DIP (Windowed) |
| Type de montage | Through-Hole | — |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| Nombre de broches | 40 | 40 |
| Statut RoHS | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: RoHS status] |
| Family | — | Altera Classic EPLD |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| Technology | — | CMOS, UV-erasable |
| Package Type | — | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | — | Industrial (-40C to +85C) |
| Logic Family | — | EPLD (Erasable PLD) |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |