EP910IPC-15 vs EP910PC-20 Comparison
Detailed side-by-side comparison of EP910IPC-15 by Altera and EP910PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-15 | EP910PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Operating Temperature | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial) |
| Package | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | EPROM programmer, JEDEC fuse map |
| Pin Count | 40 | 24 |
| RoHS Status | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: RoHS status] |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| MSL Level | — | [DATA_NEEDED: MSL level] |