EP910IPC-15 vs EP910PC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-15 sa pamamagitan ng Altera at EP910PC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-15 | EP910PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Temperature na Operasyon | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial) |
| Packhaging | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | EPROM programmer, JEDEC fuse map |
| Bilang ng Pin | 40 | 24 |
| Tindminan RoHS | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: RoHS status] |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |