EP910IPC-25 vs EP910PC-20 Comparison
Detailed side-by-side comparison of EP910IPC-25 by Intel and EP910PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-25 | EP910PC-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $12.40 |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Manufacturer | Altera (now Intel) | β |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | β |
| Usable Gates | 450 | 900 |
| Macrocells | 24 | β |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 25 ns | β |
| Maximum Frequency (fMAX) | 40 MHz | β |
| Dedicated Inputs | 12 | β |
| Bidirectional I/O Lines | 24 | β |
| Total Inputs (max) | 36 | β |
| Total Outputs (max) | 24 | β |
| Supply Voltage (VCC) | 5 V | 5 V |
| Operating Temperature | 0C to +70C (commercial grade) | 0C to +70C (commercial) |
| Package | 40-pin PDIP (PDIP-40) | PDIP-24 (PC suffix) |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Programming Method | EPROM cell (OTP / UV erasable) | EPROM programmer, JEDEC fuse map |
| Development Tool | MAX+PLUS II | β |
| Device | β | EP910 |
| Macrocell Count | β | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Pin Count | β | 24 |
| Technology | β | CMOS EPROM (UV-erasable) |
| I/O Compatibility | β | 100% TTL |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |