EP910IPC-25 vs EP910PC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-25 sa pamamagitan ng Intel at EP910PC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-25 | EP910PC-20 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Altera Classic EPLD |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | — |
| Usable Gates | 450 | 900 |
| Macrocells | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Temperature na Operasyon | 0C to +70C (commercial grade) | 0C to +70C (commercial) |
| Packhaging | 40-pin PDIP (PDIP-40) | PDIP-24 (PC suffix) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Programming Method | EPROM cell (OTP / UV erasable) | EPROM programmer, JEDEC fuse map |
| Development Tool | MAX+PLUS II | — |
| Device | — | EP910 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Bilang ng Pin | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |