EP910JC-35 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910JC-35 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-35 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $15.60 |
| Logic Family | Classic EPLD (CMOS EPROM) | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | β |
| I/O Pins | 24 | β |
| Propagation Delay (max) | 38 ns (tPD) | β |
| Maximum Clock Frequency | 28.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0C to 70C (Commercial) | 0C to +70C (commercial) |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | β |
| Mounting Type | Surface Mount (PLCC socket recommended) | Through-Hole |
| Terminal Form | J BEND | β |
| Package Code | QCCJ | β |
| Package Shape | SQUARE | β |
| Technology | CMOS EPROM, UV-erasable / OTP | β |
| RoHS Status | [DATA_NEEDED: rohs status] | β |
| Temperature Grading | COMMERCIAL | β |
| Equivalent Gates | Approx. 900 usable gates | β |
| Family | β | Classic EPLD (EP910 series) |
| Architecture | β | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | β | 900 usable gates |
| Propagation Delay (tPD) | β | 30 ns (max) |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Dedicated Inputs | β | 36 |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Supply Voltage | β | 5 V |
| Process Technology | β | CMOS |
| Programming Method | β | UV-Erasable / OTP |
| Package | β | DIP-40 (through-hole, 600 mil) |