EP910JC-35 vs EP910DC-30 比較
詳細並排比較 EP910JC-35 由 Altera 與 EP910DC-30 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910JC-35 | EP910DC-30 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| I/O Pins | 24 | — |
| Propagation Delay (max) | 38 ns (tPD) | — |
| 最大時脈頻率 | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作溫度 | 0C to 70C (Commercial) | 0C to +70C (commercial) |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| 安裝類型 | Surface Mount (PLCC socket recommended) | Through-Hole |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | — |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Dedicated Inputs | — | 36 |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| 供應電壓 | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |
| 封裝 | — | DIP-40 (through-hole, 600 mil) |