EP910JC-35 vs EP910LC-30Y Comparison
Detailed side-by-side comparison of EP910JC-35 by Altera and EP910LC-30Y by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-35 | EP910LC-30Y |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| I/O Pins | 24 | — |
| Propagation Delay (max) | 38 ns (tPD) | — |
| Maximum Clock Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Operating Temperature | 0C to 70C (Commercial) | Commercial 0C to +70C |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| Mounting Type | Surface Mount (PLCC socket recommended) | Surface Mount (PLCC socket) |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | — |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status not specified in retrieved data] |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Family | — | Altera Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Counter Frequency (fMAX) | — | 100 MHz (family maximum) |
| Supply Voltage | — | 5 V (TTL-compatible) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Package | — | PLCC-44 |
| Speed/Power Grade | — | LC (low-power, 30ns) |
| Processing Flow | — | Y (extended reliability) |
| Logic Compatibility | — | 100% TTL emulation |