EP910JC-35 vs EP910LC-30Y Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910JC-35 sa pamamagitan ng Altera at EP910LC-30Y sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910JC-35 | EP910LC-30Y |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Logic Family | Classic EPLD (CMOS EPROM) | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| I/O Pins | 24 | — |
| Propagation Delay (max) | 38 ns (tPD) | — |
| Maksimum na Taktiko ng Oras | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperature na Operasyon | 0C to 70C (Commercial) | Commercial 0C to +70C |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket recommended) | Surface Mount (PLCC socket) |
| Terminal Form | J BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Technology | CMOS EPROM, UV-erasable / OTP | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status not specified in retrieved data] |
| Temperature Grading | COMMERCIAL | — |
| Equivalent Gates | Approx. 900 usable gates | — |
| Family | — | Altera Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Counter Frequency (fMAX) | — | 100 MHz (family maximum) |
| Volte ng Pagbibigay | — | 5 V (TTL-compatible) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Packhaging | — | PLCC-44 |
| Speed/Power Grade | — | LC (low-power, 30ns) |
| Processing Flow | — | Y (extended reliability) |
| Logic Compatibility | — | 100% TTL emulation |