EP910LC-30 vs EP910LC-30Y Comparison
Detailed side-by-side comparison of EP910LC-30 by Altera and EP910LC-30Y by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30 | EP910LC-30Y |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.50 | $25.40 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 24 | β |
| Propagation Delay (tPD) | 30 ns (max) | β |
| Maximum Toggle Frequency | 62 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | β |
| Process Technology | CMOS (EPROM-based) | CMOS, UV-erasable / OTP |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| I/O Pin Count | 24 | β |
| Dedicated Input Pins | 36 (including I/O) | β |
| Product Terms per Macrocell | Up to 16 | β |
| Programming Technology | UV-erasable EPROM cell | β |
| Development Tool | Altera MAX+PLUS II | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not specified in retrieved data] |
| Family | β | Altera Classic EPLD |
| Macrocells | β | 24 |
| Usable Gates | β | 450 |
| Pin-to-Pin Delay (tPD) | β | 30 ns |
| Counter Frequency (fMAX) | β | 100 MHz (family maximum) |
| Supply Voltage | β | 5 V (TTL-compatible) |
| Package | β | PLCC-44 |
| Operating Temperature | β | Commercial 0C to +70C |
| Speed/Power Grade | β | LC (low-power, 30ns) |
| Processing Flow | β | Y (extended reliability) |
| Logic Compatibility | β | 100% TTL emulation |
| Mounting Type | β | Surface Mount (PLCC socket) |