EP910LC-30 vs EP910LC-30Y Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LC-30 disebabkan oleh Altera dan EP910LC-30Y disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910LC-30 | EP910LC-30Y |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 24 | — |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Maximum Toggle Frequency | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | — |
| Process Technology | CMOS (EPROM-based) | CMOS, UV-erasable / OTP |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | — |
| Operating Temperature Grade | Commercial (0C to +70C) | — |
| I/O Pin Count | 24 | — |
| Dedicated Input Pins | 36 (including I/O) | — |
| Product Terms per Macrocell | Up to 16 | — |
| Programming Technology | UV-erasable EPROM cell | — |
| Development Tool | Altera MAX+PLUS II | — |
| Aras MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not specified in retrieved data] |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Counter Frequency (fMAX) | — | 100 MHz (family maximum) |
| Tegangan Pemberi Arus | — | 5 V (TTL-compatible) |
| Kemasan | — | PLCC-44 |
| Suhu Operasi | — | Commercial 0C to +70C |
| Speed/Power Grade | — | LC (low-power, 30ns) |
| Processing Flow | — | Y (extended reliability) |
| Logic Compatibility | — | 100% TTL emulation |
| Jenis Pemasangan | — | Surface Mount (PLCC socket) |