EP910LC-30Y vs EP910LC-25 Comparison
Detailed side-by-side comparison of EP910LC-30Y by Altera and EP910LC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30Y | EP910LC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| Supply Voltage | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Package | PLCC-44 | 28-pin PLCC (LC suffix) |
| Operating Temperature | Commercial 0C to +70C | 0C to +70C (commercial) |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| Mounting Type | Surface Mount (PLCC socket) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS status] |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 16 |
| Technology | — | CMOS (EPROM-based) |
| Operating Voltage | — | [DATA_NEEDED: VCC range] |
| Programmable | — | Yes (EPROM, UV-erasable on windowed variants) |
| I/O Pins | — | [DATA_NEEDED: I/O count] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |