EP910LC-35 vs EP910JC-30 Comparison
Detailed side-by-side comparison of EP910LC-35 by Altera and EP910JC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-35 | EP910JC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.75 | $9.75 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Classic (EP910) | Classic EPLD (MAX-style) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | β |
| Propagation Delay (tPD) | 35 ns | β |
| Maximum Toggle Frequency | 28.6 MHz | β |
| Supply Voltage (VCC) | 5 V | β |
| Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Package | PLCC-44 (J-lead, LC suffix) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Pin Count | 44 | β |
| Programmable Flip-Flops | Yes (per macrocell) | β |
| Output Enable Control | Per macrocell | β |
| Erasure Method | UV (windowed) or OTP (plastic) | β |
| RoHS Status | Not applicable (legacy product) | [DATA_NEEDED: RoHS compliance] |
| Propagation Delay (tpd) | β | 30 ns |
| Maximum Internal Frequency (Fmax) | β | 33.3 MHz |
| Inputs | β | 36 |
| Product Terms | β | 240 |
| Outputs | β | 10 dedicated |
| Supply Voltage (Vcc) | β | 5 V |
| Supply Current (Icc) | β | [DATA_NEEDED: Icc typical / maximum] |
| Mounting Type | β | Surface Mount (socket-mountable) |
| Logic Blocks | β | 24 macrocells (AND/OR array architecture) |