EP910LC-35 vs EP910JC-30 Comparación
Comparación detallada lado a lado de EP910LC-35 por Altera y EP910JC-30 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910LC-35 | EP910JC-30 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $18,75 | $9,75 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic (EP910) | Classic EPLD (MAX-style) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Encapsulado | PLCC-44 (J-lead, LC suffix) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Recuento de pines | 44 | — |
| Programmable Flip-Flops | Yes (per macrocell) | — |
| Output Enable Control | Per macrocell | — |
| Erasure Method | UV (windowed) or OTP (plastic) | — |
| Estado RoHS | Not applicable (legacy product) | [DATA_NEEDED: RoHS compliance] |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Inputs | — | 36 |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Tipo de montaje | — | Surface Mount (socket-mountable) |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |