EP910LC44-30T vs EP910LI-30T Comparison
Detailed side-by-side comparison of EP910LC44-30T by Altera and EP910LI-30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC44-30T | EP910LI-30T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Logic Type | PAL-type CMOS EPLD (OT PLD) | — |
| Macrocells | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 33 ns | 30 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Dedicated Inputs | 12 | 10 |
| I/O Lines | 24 (bidirectional) | — |
| Total Inputs | 36 | — |
| Total Outputs | 24 | — |
| External Clock Inputs | 2 | — |
| Programming Technology | CMOS, UV-erasable (windowed package in family) | — |
| Security Bit | Programmable (logic readback protection) | — |
| Operating Temperature Grade | Commercial | — |
| Package | PQCC-44 (Plastic Leaded Chip Carrier, J-bend) | PQCC-44 (J-lead) |
| Terminal Form | J-BEND | — |
| Package Code | QCCJ | — |
| Mounting Type | Surface Mount | Surface Mount |
| Family | — | Altera Classic EPLD |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Clock-to-Output (tCO) | — | [DATA_NEEDED: tCO] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| I/O Pins | — | 24 |
| Operating Temperature | — | -40C to +85C (Industrial) |
| Technology | — | CMOS, UV-erasable |
| Supply Voltage | — | [DATA_NEEDED: VCC] |
| Programming Method | — | EPROM (UV-erasable) via Altera Logic Programmer |
| RoHS Status | — | [DATA_NEEDED: RoHS] |
| Lead-Free | — | [DATA_NEEDED: Lead-free] |