EP910LC44-35 vs EP910LC-35 Comparison
Detailed side-by-side comparison of EP910LC44-35 by Intel and EP910LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC44-35 | EP910LC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Classic EPLD (OT sub-family) | Classic (EP910) |
| Architecture | PAL-type AND/OR array | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Propagation Delay (tPD) | 35 ns (max) | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | — |
| I/O Pins | 24 | — |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | 44-pin PLCC (J-leaded) | PLCC-44 (J-lead, LC suffix) |
| Mounting Type | Surface Mount | — |
| Process Technology | CMOS | — |
| Programmability | UV-erasable (windowed ceramic) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Technology | — | CMOS EPROM |
| Pin Count | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |
| RoHS Status | — | Not applicable (legacy product) |