EP910LC44-35 vs EP910LC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC44-35 sa pamamagitan ng Intel at EP910LC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC44-35 | EP910LC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD (OT sub-family) | Classic (EP910) |
| Architecture | PAL-type AND/OR array | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Propagation Delay (tPD) | 35 ns (max) | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | — |
| I/O Pins | 24 | — |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Packhaging | 44-pin PLCC (J-leaded) | PLCC-44 (J-lead, LC suffix) |
| Uri ng Pagpapasok | Surface Mount | — |
| Process Technology | CMOS | — |
| Programmability | UV-erasable (windowed ceramic) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Technology | — | CMOS EPROM |
| Bilang ng Pin | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |
| Tindminan RoHS | — | Not applicable (legacy product) |