EP910LC44-40 vs EP910LC44-35 Comparison
Detailed side-by-side comparison of EP910LC44-40 by Altera and EP910LC44-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC44-40 | EP910LC44-35 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | Altera Classic EPLD | Classic EPLD (OT sub-family) |
| Macrocells | 24 | 24 |
| Product Terms (Total) | 240 | — |
| I/O Pins | 24 (bidirectional) | 24 |
| Dedicated Inputs | 12 | — |
| Total Inputs | 36 | 36 |
| Global Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | 35 ns (max) |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (single supply) |
| Technology | CMOS, UV-erasable EPROM | — |
| Logic Compatibility | TTL-compatible I/O | — |
| Package | 44-pin PLCC (Plastic Leaded Chip Carrier) | 44-pin PLCC (J-leaded) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | JEDEC file via LP6/MP9 or compatible programmer | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | — |
| Architecture | — | PAL-type AND/OR array |
| Usable Gates | — | 450 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Global Clocks | — | 2 |
| Process Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed ceramic) |