EP910LC44 vs EP910LC-40 Comparison
Detailed side-by-side comparison of EP910LC44 by Altera and EP910LC-40 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910LC44
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 β Last Time BuyRochester Electronics
EP910LC-40
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 ObsoleteSpecification Comparison
| Parameter | EP910LC44 | EP910LC-40 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.95 | $52.00 |
| Product Family | Classic EPLD (EP910 Series) | β |
| Manufacturer | Altera Corporation (now Intel PSG) | Rochester Electronics (Altera original) |
| Device Type | Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 24 | 24 |
| Total Product Terms | 240 | β |
| Dedicated Inputs | 12 | 4 |
| I/O Pins | 24 | β |
| Total Input Pins | 36 (12 dedicated + 24 I/O as inputs) | β |
| Global Clock Inputs | 2 | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| Propagation Delay (LC grade) | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] | β |
| Propagation Delay (LC-30 grade) | 33 ns (per EP910LC44-30 verified data) | β |
| Process Technology | CMOS | β |
| Package | 44-pin PLCC (J-leaded) | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| Operating Temperature | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] | β |
| Programming Method | EPROM (erasable UV for ceramic; OTP for plastic PLCC) | Altera Logic Programmer (PLAD-J), 4-wire serial |
| Architecture | AND-OR sum-of-products with programmable macrocell feedback | β |
| Logic Compatibility | TTL-compatible CMOS I/O | β |
| RoHS Status | [DATA_NEEDED: not stated in verified data] | Not applicable (legacy) |
| Device Family | β | Altera Classic EPLD - EP910 |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | β | 450 |
| Logic Array Blocks | β | 2 (12 macrocells each) |
| Propagation Delay (tPD) | β | 40 ns |
| Maximum Toggle Frequency (fMAX) | β | 25 MHz |
| User I/O Pins | β | 36 |
| Technology | β | CMOS EPROM |
| Operating Temperature (Commercial) | β | 0 C to +70 C |
| Lead-Free Status | β | Not applicable |