EP910LC44 vs EP910LC-40 موازنہ
تفصیلی ساتھ ساتھ موازنہ از EP910LC44 بذریعہ Altera اور EP910LC-40 بذریعہ Rochester Electronics. اہم خصوصیات، برقی پیرامیٹرز، پیکیجنگ، لائف سائیکل اسٹیٹس، قیمتوں اور دستیابی کا موازنہ کریں تاکہ آپ کی ڈیزائن ضروریات کے لیے بہترین کمپوننٹ کا تعین ہو سکے۔
Altera
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 ⚠ آخری بار خریداریRochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsoleteخصوصیات کا موازنہ
| پیرامیٹر | EP910LC44 | EP910LC-40 |
|---|---|---|
| برانڈ | Altera | Rochester Electronics |
| زمرہ | FPGA & CPLD | FPGA & CPLD |
| لائف سائیکل کی حالت | آخری بار خریداری | Obsolete |
| Product Family | Classic EPLD (EP910 Series) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | Rochester Electronics (Altera original) |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Total Product Terms | 240 | — |
| Dedicated Inputs | 12 | 4 |
| I/O Pins | 24 | — |
| Total Input Pins | 36 (12 dedicated + 24 I/O as inputs) | — |
| Global Clock Inputs | 2 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| Propagation Delay (LC grade) | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] | — |
| Propagation Delay (LC-30 grade) | 33 ns (per EP910LC44-30 verified data) | — |
| Process Technology | CMOS | — |
| پیکیج | 44-pin PLCC (J-leaded) | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| آپریٹنگ درجہ حرارت | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] | — |
| Programming Method | EPROM (erasable UV for ceramic; OTP for plastic PLCC) | Altera Logic Programmer (PLAD-J), 4-wire serial |
| Architecture | AND-OR sum-of-products with programmable macrocell feedback | — |
| Logic Compatibility | TTL-compatible CMOS I/O | — |
| RoHS اسٹیٹس | [DATA_NEEDED: not stated in verified data] | Not applicable (legacy) |
| Device Family | — | Altera Classic EPLD - EP910 |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Logic Array Blocks | — | 2 (12 macrocells each) |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Toggle Frequency (fMAX) | — | 25 MHz |
| User I/O Pins | — | 36 |
| Technology | — | CMOS EPROM |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| Lead-Free Status | — | Not applicable |