EP910LI-20T vs EP910LI-12 Comparison
Detailed side-by-side comparison of EP910LI-20T by Altera and EP910LI-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-20T | EP910LI-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD (Altera) | — |
| Macrocells | 24 | 24 |
| Logic Array Blocks (LABs) | 4 | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 20 | 24 |
| Propagation Delay (tPD) | 20 ns | 12 ns |
| Maximum Frequency (fMAX) | 95 MHz | 76.9 MHz |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V typical) |
| Programming Technology | CMOS EPROM (UV-erasable) | — |
| Programming Voltage | 21 V | — |
| Package | CDIP-20 (ceramic DIP, through-hole) | 28-PLCC (windowed ceramic, J-Lead) |
| Speed Grade | -20 | — |
| Operating Temperature | -40 C to +85 C (industrial) | -40C to +85C (industrial) |
| Mounting Type | Through-hole | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | non_compliant (ceramic windowed package) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Device Family | — | Altera Classic EPLD |
| Usable Gates | — | 450 |
| Inputs (with input registers) | — | 36 |
| Process Technology | — | 1.0-micron CMOS EPROM |
| Power Dissipation (typical) | — | 200 mW at 5 V |
| Programming Method | — | UV-erasable via windowed package |
| Logic Compatibility | — | TTL-compatible I/O |