EP910LI-35 vs EP910LI-12 Comparison
Detailed side-by-side comparison of EP910LI-35 by Altera and EP910LI-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-35 | EP910LI-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Series | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | — |
| Operating Temperature | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial) |
| Package | 44-pin PLCC (J-lead) | 28-PLCC (windowed ceramic, J-Lead) |
| Process Technology | CMOS EPROM | 1.0-micron CMOS EPROM |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| Mounting Type | Surface Mount | — |
| Lead Pitch | 1.27 mm | — |
| Device Family | — | Altera Classic EPLD |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Frequency (fMAX) | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V typical) |
| I/O Pins | — | 24 |
| Inputs (with input registers) | — | 36 |
| Power Dissipation (typical) | — | 200 mW at 5 V |
| Programming Method | — | UV-erasable via windowed package |
| Logic Compatibility | — | TTL-compatible I/O |
| RoHS Status | — | non_compliant (ceramic windowed package) |