EP910LI-35 vs EP910LI-12 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35 sa pamamagitan ng Altera at EP910LI-12 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35 | EP910LI-12 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Series | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| Volte ng Pagbibigay | 5 V (4.75 V to 5.25 V) | — |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial) |
| Packhaging | 44-pin PLCC (J-lead) | 28-PLCC (windowed ceramic, J-Lead) |
| Process Technology | CMOS EPROM | 1.0-micron CMOS EPROM |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Lead Pitch | 1.27 mm | — |
| Device Family | — | Altera Classic EPLD |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Frequency (fMAX) | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V typical) |
| I/O Pins | — | 24 |
| Inputs (with input registers) | — | 36 |
| Power Dissipation (typical) | — | 200 mW at 5 V |
| Programming Method | — | UV-erasable via windowed package |
| Logic Compatibility | — | TTL-compatible I/O |
| Tindminan RoHS | — | non_compliant (ceramic windowed package) |