EP910LI-35BF vs EP910LC-35 Comparison
Detailed side-by-side comparison of EP910LI-35BF by Altera and EP910LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-35BF | EP910LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Part Number Base | EP910 | — |
| Logic Density | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V |
| Package | 44-pin PLCC (J-lead) | PLCC-44 (J-lead, LC suffix) |
| Operating Temperature Range | Industrial (LI suffix) | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) | — |
| Output Polarity Control | Programmable XOR per macrocell | — |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell | — |
| TTL Compatibility | 100% TTL emulation | — |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic (EP910) |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Operating Temperature | — | 0C to +70C (commercial) |
| Pin Count | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |
| RoHS Status | — | Not applicable (legacy product) |