EP910LI-35BF vs EP910LC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35BF sa pamamagitan ng Altera at EP910LC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35BF | EP910LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Part Number Base | EP910 | — |
| Logic Density | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V |
| Packhaging | 44-pin PLCC (J-lead) | PLCC-44 (J-lead, LC suffix) |
| Hanay ng Temperature na Operasyon | Industrial (LI suffix) | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) | — |
| Output Polarity Control | Programmable XOR per macrocell | — |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell | — |
| TTL Compatibility | 100% TTL emulation | — |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic (EP910) |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Bilang ng Pin | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |
| Tindminan RoHS | — | Not applicable (legacy product) |