EP910LI-35H vs EP910LI-30T Comparison
Detailed side-by-side comparison of EP910LI-35H by Intel and EP910LI-30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-35H | EP910LI-30T |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD (EP910) | Altera Classic EPLD |
| Logic Capacity | 900 usable gates | — |
| Macro Cells | 24 | — |
| Speed Grade (tPD) | 35 ns | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCC) | 5 V (±10%) | — |
| Technology | CMOS, UV-erasable EPROM cell | CMOS, UV-erasable |
| Package | 44-pin PLCC (J-lead) | PQCC-44 (J-lead) |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Standby Current | [DATA_NEEDED: ICCSB] | — |
| Active Supply Current | [DATA_NEEDED: ICC] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | unknown | [DATA_NEEDED: RoHS] |
| Lead-Free Option (H suffix) | Yes (H suffix) | — |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 30 ns |
| Clock-to-Output (tCO) | — | [DATA_NEEDED: tCO] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 24 |
| Supply Voltage | — | [DATA_NEEDED: VCC] |
| Programming Method | — | EPROM (UV-erasable) via Altera Logic Programmer |
| Lead-Free | — | [DATA_NEEDED: Lead-free] |