EP910LI-50 vs EP910LI-40 Comparison
Detailed side-by-side comparison of EP910LI-50 by Altera and EP910LI-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-50 | EP910LI-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 50 ns | 40 ns |
| Package Type | CERDIP-40 (L) | — |
| Package Pin Count | 40 | — |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial, I-suffix) |
| Technology | CMOS, UV-erasable EPROM | Low-power CMOS (L-suffix) |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 bidirectional |
| Programming Method | EPROM programmer (UV-erasable window) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (windowed ceramic PLCC, legacy) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Product Family | — | Classic EPLD - EP910 series |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Dedicated Inputs | — | 12 |
| Maximum Logic Inputs | — | 36 |
| Product Terms | — | 240 |
| Package | — | PLCC-44 (J-lead, windowed ceramic) |
| Mounting Type | — | Surface Mount (socket-compatible) |
| Programmability | — | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | — | Obsolete - replaced by MAX 7000 / MAX II CPLD family |