EP910PC-0 vs EP910PC-35 Comparison
Detailed side-by-side comparison of EP910PC-0 by Altera and EP910PC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-0 | EP910PC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Classic EPLD |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Logic Blocks | 6 (4 macrocells each) | — |
| Dedicated Inputs | 10 | 12 |
| I/O Pins | 24 | 24 |
| Package | PDIP-40 (Plastic DIP, 40-pin) | 40-pin PDIP (Plastic DIP) |
| Speed Grade | -0 (slowest) | — |
| Supply Voltage | 5 V (single supply) | 5 V |
| Process Technology | CMOS | — |
| Logic Compatibility | 100% TTL emulation | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV-erasable / OTP | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Total Inputs | — | 36 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Counter Frequency | — | 37 MHz |
| Internal Performance Frequency | — | 100 MHz |
| Technology | — | CMOS, UV-erasable/OTP |
| Architecture | — | PAL-type sum-of-products, AND/OR array |
| Compliance / RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |