EP910PC-20 vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910PC-20 by Altera and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-20 | EP910PC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.40 | $6.50 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | β |
| Usable Gates | 900 | ~450 |
| Macrocell Count | [DATA_NEEDED: macrocell count] | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Package | PDIP-24 (PC suffix) | PDIP-40 (plastic DIP, 0.6 inch) |
| Pin Count | 24 | β |
| Supply Voltage (VCC) | 5 V | 5 V Β±10% |
| Technology | CMOS EPROM (UV-erasable) | β |
| I/O Compatibility | 100% TTL | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | EPROM programmer, JEDEC fuse map | β |
| Mounting Type | Through-Hole (DIP) | Through-hole DIP |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead, PDIP package) |
| Macrocells | β | 24 |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Logic Inputs | β | 36 dedicated |
| I/O Pins | β | 12 bidirectional |
| Logic Array Blocks (LABs) | β | 4 |
| Programming Technology | β | UV-erasable EPROM cell |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |