EP910PC-20T vs EP910PC-15T Comparison
Detailed side-by-side comparison of EP910PC-20T by Altera and EP910PC-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-20T | EP910PC-15T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Unknown | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.70 | $14.20 |
| Device Type | EPLD | β |
| Family | Classic EPLD | Altera Classic EPLD |
| Fabrication Technology | CMOS | β |
| Logic Integration | 300 to 900 usable gates | β |
| Logic Emulation | 100% TTL emulation | β |
| Application Function | High-speed, low-power logic integration | β |
| Programmable Device Class | Erasable programmable logic device | β |
| Device Family | Altera Classic EPLD Family | β |
| Speed Grade | 20 ns | -15 (15 ns) |
| Package Code | PC | β |
| Package Pin Count | [DATA_NEEDED: package pin count] | β |
| Package Dimensions | [DATA_NEEDED: package dimensions] | β |
| Supply Voltage | [DATA_NEEDED: operating supply voltage] | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Count | [DATA_NEEDED: I/O count] | β |
| Internal Logic Capacity | 300 to 900 usable gates | β |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | β |
| Programming Interface | [DATA_NEEDED: programming interface] | β |
| Programming Voltage | [DATA_NEEDED: programming voltage] | β |
| Mounting Technology | [DATA_NEEDED: mounting technology] | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | unknown | β |
| AEC-Q100 Qualification | not_applicable | β |
| Lead-Free Status | unknown | β |
| Halogen-Free Status | unknown | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | β | 24 |
| Dedicated Input Pins | β | 10 |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Supply Voltage (VCC) | β | 5 V (nominal) |
| Technology | β | CMOS, UV-erasable / OTP |
| Package | β | 40-pin PDIP (Plastic DIP) |
| Mounting Type | β | Through-hole (DIP) |
| Output Drive Current | β | [DATA_NEEDED: IOL per output] |
| Logic Capacity | β | 24 macrocells / 72 product terms (typical Classic architecture) |
| Programming Method | β | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Security Bit | β | Yes (design protection) |
| Tape and Reel | β | Yes (suffix T) |