EP910PC-20T vs EP910PC-15T তুলনা
. বিস্তৃত সাথে-সাথে তুলনা EP910PC-20T নির্দিষ্ট Altera ও EP910PC-15T নির্দিষ্ট Altera. প্রধান বিশেষত্ব, বৈদ্যুতিক প্রাকৃতিক, প্যাকেজিং, জীবনচক্র অবস্থা, মূল্যাঙ্কন, ও পরিসীমা কোন অপশনটির কেন্দ্রীয় নির্ধারণ করুন
বিশিষ্টতা তুলনা
| পারামিটার | EP910PC-20T | EP910PC-15T |
|---|---|---|
| ব্র্যান্ড | Altera | Altera |
| ক্যাটাগরি | FPGA & CPLD | FPGA & CPLD |
| লাইফসাইকেল স্ট্যাটাস | Unknown | Obsolete |
| Device Type | EPLD | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Fabrication Technology | CMOS | — |
| Logic Integration | 300 to 900 usable gates | — |
| Logic Emulation | 100% TTL emulation | — |
| Application Function | High-speed, low-power logic integration | — |
| Programmable Device Class | Erasable programmable logic device | — |
| Device Family | Altera Classic EPLD Family | — |
| Speed Grade | 20 ns | -15 (15 ns) |
| Package Code | PC | — |
| Package Pin Count | [DATA_NEEDED: package pin count] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| সাপ্লাই ভোল্টেজ | [DATA_NEEDED: operating supply voltage] | — |
| অপারেটিং তাপমাত্রা | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Count | [DATA_NEEDED: I/O count] | — |
| Internal Logic Capacity | 300 to 900 usable gates | — |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | — |
| Programming Interface | [DATA_NEEDED: programming interface] | — |
| Programming Voltage | [DATA_NEEDED: programming voltage] | — |
| Mounting Technology | [DATA_NEEDED: mounting technology] | — |
| RoHS স্ট্যাটাস | unknown | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | — | 24 |
| Dedicated Input Pins | — | 10 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Technology | — | CMOS, UV-erasable / OTP |
| প্যাকেজ | — | 40-pin PDIP (Plastic DIP) |
| মাউন্টিং টাইপ | — | Through-hole (DIP) |
| Output Drive Current | — | [DATA_NEEDED: IOL per output] |
| Logic Capacity | — | 24 macrocells / 72 product terms (typical Classic architecture) |
| Programming Method | — | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Security Bit | — | Yes (design protection) |
| Tape and Reel | — | Yes (suffix T) |