EP910PC-20T vs EP910PC30T Comparison
Detailed side-by-side comparison of EP910PC-20T by Altera and EP910PC30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-20T | EP910PC30T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Unknown | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.70 | $8.85 |
| Device Type | EPLD | β |
| Family | Classic EPLD | Altera Classic EPLD |
| Fabrication Technology | CMOS | β |
| Logic Integration | 300 to 900 usable gates | β |
| Logic Emulation | 100% TTL emulation | β |
| Application Function | High-speed, low-power logic integration | β |
| Programmable Device Class | Erasable programmable logic device | β |
| Device Family | Altera Classic EPLD Family | β |
| Speed Grade | 20 ns | -30 (30 ns tPD) |
| Package Code | PC | β |
| Package Pin Count | [DATA_NEEDED: package pin count] | β |
| Package Dimensions | [DATA_NEEDED: package dimensions] | β |
| Supply Voltage | [DATA_NEEDED: operating supply voltage] | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| I/O Count | [DATA_NEEDED: I/O count] | β |
| Internal Logic Capacity | 300 to 900 usable gates | β |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | β |
| Programming Interface | [DATA_NEEDED: programming interface] | β |
| Programming Voltage | [DATA_NEEDED: programming voltage] | β |
| Mounting Technology | [DATA_NEEDED: mounting technology] | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | unknown | β |
| AEC-Q100 Qualification | not_applicable | β |
| Lead-Free Status | unknown | β |
| Halogen-Free Status | unknown | β |
| Device Series | β | EP910 |
| Number of Macrocells | β | 24 |
| Number of I/O Pins | β | 24 |
| Number of Dedicated Inputs | β | 12 |
| Maximum Product Terms | β | 240 |
| Propagation Delay (tPD) | β | 30 ns |
| Maximum Clock Frequency (fMAX) | β | 33.3 MHz |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| Process Technology | β | CMOS |
| Programmable Logic Architecture | β | PAL-type sum-of-products, EPLD |
| Package | β | 24-pin PDIP (PC) |
| Mounting Type | β | Through-Hole (THT) |
| Programming Technology | β | EPROM (OTP in plastic package, UV-erasable in windowed package) |
| Pin Count | β | 24 |