EP910PC-20T vs EP910PC30T 比較

詳細並排比較 EP910PC-20T 由 Altera 與 EP910PC30T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP910PC-20T EP910PC30T
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Unknown Obsolete
Device Type EPLD —
Family Classic EPLD Altera Classic EPLD
Fabrication Technology CMOS —
Logic Integration 300 to 900 usable gates —
Logic Emulation 100% TTL emulation —
Application Function High-speed, low-power logic integration —
Programmable Device Class Erasable programmable logic device —
Device Family Altera Classic EPLD Family —
Speed Grade 20 ns -30 (30 ns tPD)
Package Code PC —
Package Pin Count [DATA_NEEDED: package pin count] —
Package Dimensions [DATA_NEEDED: package dimensions] —
供應電壓 [DATA_NEEDED: operating supply voltage] —
工作溫度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
I/O Count [DATA_NEEDED: I/O count] —
Internal Logic Capacity 300 to 900 usable gates —
Supported Logic Integration Multiple PAL- and GAL-type devices —
Programming Interface [DATA_NEEDED: programming interface] —
Programming Voltage [DATA_NEEDED: programming voltage] —
Mounting Technology [DATA_NEEDED: mounting technology] —
RoHS 狀態 unknown [DATA_NEEDED: RoHS compliance status]
REACH Status unknown —
AEC-Q100 Qualification not_applicable —
Lead-Free Status unknown —
Halogen-Free Status unknown —
Device Series — EP910
Number of Macrocells — 24
Number of I/O Pins — 24
Number of Dedicated Inputs — 12
Maximum Product Terms — 240
Propagation Delay (tPD) — 30 ns
Maximum Clock Frequency (fMAX) — 33.3 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Process Technology — CMOS
Programmable Logic Architecture — PAL-type sum-of-products, EPLD
封裝 — 24-pin PDIP (PC)
安裝類型 — Through-Hole (THT)
Programming Technology — EPROM (OTP in plastic package, UV-erasable in windowed package)
腳位數 — 24

資料表與資源

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