EP910PC-25 vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910PC-25 by Altera and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-25 | EP910PC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.92 | $6.50 |
| Product Family | Classic EPLD | β |
| Usable Gates | 900 | ~450 |
| Integration Gates (typical) | 4800 | β |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | β |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V Β±10% |
| Technology | CMOS EPROM | β |
| Package | PDIP-24 (Plastic DIP) | PDIP-40 (plastic DIP, 0.6 inch) |
| Pin Count | 24 | β |
| Dedicated Inputs | 10 | β |
| Dedicated I/O Pins | 12 | β |
| TTL Compatibility | 100% TTL emulation | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | β |
| Family | β | Altera Classic EPLD |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Logic Inputs | β | 36 dedicated |
| I/O Pins | β | 12 bidirectional |
| Logic Array Blocks (LABs) | β | 4 |
| Programming Technology | β | UV-erasable EPROM cell |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |
| RoHS Status | β | Non-compliant (contains lead, PDIP package) |
| Mounting Type | β | Through-hole DIP |