EP910PC-25 vs EP910PC-30 比較
詳細並排比較 EP910PC-25 由 Altera 與 EP910PC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-25 | EP910PC-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | ~450 |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V ±10% |
| Technology | CMOS EPROM | — |
| 封裝 | PDIP-24 (Plastic DIP) | PDIP-40 (plastic DIP, 0.6 inch) |
| 腳位數 | 24 | — |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Altera Classic EPLD |
| Pin-to-Pin Propagation Delay (tPD) | — | 30 ns |
| Maximum Counter Frequency (fCNT) | — | 33.3 MHz |
| Logic Inputs | — | 36 dedicated |
| I/O Pins | — | 12 bidirectional |
| Logic Array Blocks (LABs) | — | 4 |
| Programming Technology | — | UV-erasable EPROM cell |
| TTL Emulation | — | 100% TTL-compatible |
| Power Dissipation | — | [DATA_NEEDED: power dissipation mW] |
| RoHS 狀態 | — | Non-compliant (contains lead, PDIP package) |
| 安裝類型 | — | Through-hole DIP |