EP910PI-20T vs EP910PI-15T Comparison
Detailed side-by-side comparison of EP910PI-20T by Intel and EP910PI-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-20T | EP910PI-15T |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| Number of Pins | 40 | — |
| Package | PDIP-40 (PI) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Technology | CMOS EPROM (UV-erasable) | CMOS EEPROM (electrically erasable) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Programming | Standard EPROM programmer, JEDEC map | JEDEC-standard, serial/parallel programmer |
| RoHS Status | unknown | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lifecycle Status | Not Recommended for New Designs (NRND) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Supply Voltage | — | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | — | 15 ns max (speed grade -15) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |