EP910PI-20T vs EP910PI-15T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-20T sa pamamagitan ng Intel at EP910PI-15T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-20T | EP910PI-15T |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| Bilang ng Pins | 40 | — |
| Packhaging | PDIP-40 (PI) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Technology | CMOS EPROM (UV-erasable) | CMOS EEPROM (electrically erasable) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Programming | Standard EPROM programmer, JEDEC map | JEDEC-standard, serial/parallel programmer |
| Tindminan RoHS | unknown | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Katayuan ng Lifecycle | Not Recommended for New Designs (NRND) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Volte ng Pagbibigay | — | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | — | 15 ns max (speed grade -15) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |