EP910PI-25T vs EP910PI-15T Comparison
Detailed side-by-side comparison of EP910PI-25T by Altera and EP910PI-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-25T | EP910PI-15T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Altera Classic EPLD Family | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Equivalent Gates | 900 (SSI/MSI equivalent) | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EEPROM (electrically erasable) |
| Package | 40-pin PDIP (600-mil) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Programming | UV-erasable | JEDEC-standard, serial/parallel programmer |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Static Power | <100 mW (typical CMOS) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Supply Voltage | — | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | — | 15 ns max (speed grade -15) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |