EP910PI-25T vs EP910PI-15T Comparaison
Comparaison détaillée côte à côte de EP910PI-25T par Altera et EP910PI-15T par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PI-25T | EP910PI-15T |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $10,95 |
| Family | Altera Classic EPLD Family | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Equivalent Gates | 900 (SSI/MSI equivalent) | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EEPROM (electrically erasable) |
| Boîtier | 40-pin PDIP (600-mil) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Programming | UV-erasable | JEDEC-standard, serial/parallel programmer |
| Type de montage | Through-Hole (DIP) | Through-Hole |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Static Power | <100 mW (typical CMOS) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Tension d'alimentation | — | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | — | 15 ns max (speed grade -15) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |